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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTE53N50E/D ISOTOPTM TMOS E-FET.TM Power Field Effect Transistor N-Channel Enhancement-Mode Silicon Gate This advanced high voltage TMOS E-FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a drain-to-source diode with fast recovery time. Designed for high voltage, high speed switching applications such as power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * 2500 V RMS Isolated Isotop Package * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * Very Low Internal Parasitic Inductance * IDSS and VDS(on) Specified at Elevated Temperature * U. L. Recognized, File #E69369 G S Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Designer'sTM Data Sheet MTE53N50E Motorola Preferred Device TMOS POWER FET 53 AMPERES 500 VOLTS RDS(on) = 0.080 OHM (R) 4 1 2 3 D SOT-227B 1. 2. 3. 4. Source Gate Drain Source 2 MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage -- Continuous Gate-Source Voltage -- Non-Repetitive (tp 10 ms) Drain Current -- Continuous Drain Current -- Continuous @ 100C Drain Current -- Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy (VDD = 25 Vdc, VGS = 10 Vdc, IL= 53 Apk, L = 0.29 mH, RG =25) RMS Isolation Voltage Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Value 500 500 20 40 53 33 210 460 3.70 - 40 to 150 400 Unit Vdc Vdc Vdc Vpk Adc Watts W/C C mJ VISO RJC RJA TL 2500 0.28 62.5 260 Vac C/W C Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design. E-FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. ISOTOP is a trademark of SGS-THOMSON Microelectronics. Preferred devices are Motorola recommended choices for future use and best overall value. REV 2 (c)Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1996 1 MTE53N50E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 500 Vdc, VGS = 0 Vdc) (VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 26.5 Adc) Drain-Source On-Voltage (VGS = Vdc) (ID = 53 Adc) (ID = 26.5 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 26.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge ( (VDS = 400 Vdc, ID = 53 Adc, Vd , Ad , VGS = 10 Vdc) Vdc, Adc, (VDD = 250 Vd ID = 53 Ad VGS = 10 Vdc Vdc, RG = 4.7 ) ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (1) (IS = 53 Adc, VGS = 0 Vdc) (IS = 53 Adc, VGS = 0 Vdc, TJ = 125C) VSD -- -- trr (IS = 53 Adc, VGS = 0 Vdc, Ad , Vd , ( dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to center of die) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. LD -- -- LS -- 3.5 5.0 5.0 -- -- -- nH nH ta tb QRR -- -- -- -- 0.95 0.90 720 460 260 15 1.3 -- -- -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 67 322 362 310 474 86 206 148 -- -- -- -- 700 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vdc Vdc f = 1.0 MHz) Ciss Coss Crss -- -- -- 14400 1560 240 -- -- -- pF VGS(th) 2.0 -- RDS(on) VDS(on) -- -- gFS 25 -- -- 45 4.8 4.3 -- mhos -- 3.2 -- 63 4.0 -- 80 Vdc mV/C mOhm Vdc V(BR)DSS 500 -- IDSS -- -- IGSS -- -- -- -- 10 100 200 nAdc 560 550 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit Reverse Recovery Time 2 Motorola TMOS Power MOSFET Transistor Device Data MTE53N50E TYPICAL ELECTRICAL CHARACTERISTICS 120 TJ = 25C I D , DRAIN CURRENT (AMPS) 100 80 60 40 20 4V 0 0 1 8 3 5 2 4 6 7 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 9 0 2 3 4 5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 8V 7V 6V 5V VGS = 10 V I D , DRAIN CURRENT (AMPS) 120 VDS 10 V 100 80 60 40 25C 20 TJ = - 55C 100C Figure 1. On-Region Characteristics RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) Figure 2. Transfer Characteristics 0.16 VGS = 10 V 0.12 TJ = 100C 0.085 TJ = 25C 0.08 0.075 VGS = 10 V 0.07 15 V 0.08 25C 0.04 - 55C 0.065 0 0 20 40 60 80 ID, DRAIN CURRENT (AMPS) 100 120 0.06 0 20 40 60 80 ID, DRAIN CURRENT (AMPS) 100 120 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.5 VGS = 10 V ID = 26.5 A 100000 VGS = 0 V 10000 I DSS, LEAKAGE (nA) TJ = 125C 100C 2 1.5 1000 1 100 25C 10 0.5 0 - 50 - 25 0 50 100 25 75 TJ, JUNCTION TEMPERATURE (C) 125 150 1 0 100 200 300 400 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 500 Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 3 MTE53N50E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 60000 VDS = 0 V 50000 C, CAPACITANCE (pF) 40000 30000 20000 10000 Crss 0 10 5 VGS 0 VDS 5 10 15 20 25 Coss Crss Ciss Ciss C, CAPACITANCE (pF) VGS = 0 V TJ = 25C 100000 VGS = 0 V Ciss 10000 TJ = 25C 1000 Coss 100 Crss 10 10 100 DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation Figure 7b. High Voltage Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data MTE53N50E VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 Q3 0 100 200 300 Qg, TOTAL GATE CHARGE (nC) VDS 400 Q1 Q2 ID = 53 A TJ = 25C QT 420 350 VGS 280 210 140 70 0 500 10000 VDD = 250 V ID = 53 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) 1000 td(off) tr tf td(on) 100 10 1 10 RG, GATE RESISTANCE (OHMS) 100 Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. 60 50 I S , SOURCE CURRENT (AMPS) 40 30 20 10 0 0.5 VGS = 0 V TJ = 25C 0.6 0.7 0.8 0.9 1 1.1 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current Motorola TMOS Power MOSFET Transistor Device Data 5 MTE53N50E SAFE OPERATING AREA EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 1000 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 400 350 300 250 200 150 100 50 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 ID = 53 A 100 100 s 1 ms 10 10 ms dc 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 100 10 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 0.1 0.1 Figure 11. Maximum Rated Forward Biased Safe Operating Area 1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature D = 0.5 0.2 0.1 0.05 0.02 0.1 0.01 0.01 CHIP JUNCTION 0.0315 0.0318 F 0.1856 0.1239 F 0.0629 0.9536 F AMBIENT 0.001 SINGLE PULSE 0.0001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 1.0E+00 1.0E+01 Figure 13. Thermal Response di/dt IS trr ta tb TIME tp IS 0.25 IS Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTE53N50E PACKAGE DIMENSIONS A B C H L R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. MILLIMETERS MIN MAX 31.50 31.70 7.80 8.20 4.10 4.30 14.90 15.10 30.10 30.30 38.00 38.20 4.00 11.80 12.20 8.90 9.10 12.60 12.80 25.20 25.40 1.95 2.05 4.10 0.75 0.85 5.50 INCHES MIN MAX 1.240 1.248 0.307 0.322 0.161 0.169 0.586 0.590 1.185 1.193 1.496 1.503 0.157 0.464 0.480 0.350 0.358 0.496 0.503 0.992 1.000 0.076 0.080 0.157 0.030 0.033 0.217 Q G 4 1 3 2 MN D E F Recommended screw torque: 1.3" 0.2 Nm Maximum screw torque: 1.5 Nm P S STYLE 1: PIN 1. 2. 3. 4. DIM A B C D E F G H L M N P Q R S SOURCE GATE DRAIN SOURCE 2 SOT-227B Motorola TMOS Power MOSFET Transistor Device Data 7 MTE53N50E Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 8 Motorola TMOS Power MOSFET Transistor MTE53N50E/D Device Data *MTE53N50E/D* |
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